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北京三尼阳光科技发展有限公司
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Thismoduleisanidealcomponentforbuildingboxcaraveragersystems
This module is an ideal component for building boxcar averager systems. It includes a wide bandwidth variable gain AC/DC coupled input amplifier with continuous input offset adjustment and a high speed sampling gate with variable width and delay controls. It operates in normal or two baseline sampling modes and features a switch-selected choice of how many samples are included in the averaging process. Separate outputs for the average and last sample taken are also provided. A gate monitor supplies a synchronized gate output pulse for application to an oscilloscope trigger or for referencing associated processing electronics. Trigger input is ECL or TTL or can be derived from the module’s own adjustable trigger generator.
Signal Channel | |||
Mode | Normal or Baseline Sample, with baseline control via output or input signal. | ||
Sensitivity | ±20 mV to ±2 V full scale in a 1-2-5 sequence | ||
Coupling | AC/DC | ||
Impedance | 50 Ω // 10 pF DC only 1 MΩ // 30 pF DC or AC | ||
Maximum Input without damage | 50 Ω: ±5 V 1 MΩ: ±100 V (AC coupled mode) | ||
Offset | ±10 × FS via 20-turn potentiometer | ||
Overload indicator | LED lights for signals > 1.1 x FS | ||
Overload Recovery Time | Recovers after 1 trigger for x10 overload | ||
Gain Drift | 0.5% /°C, gate width > 30 ns; 1.0% /°C, gate width < 10 ns | ||
DC Drift (referred to input) | 0.2%/°C, gate width > 20 ns; 1.0%/°C, gate width < 20 ns | ||
Bandwidth | DC to 450 MHz (50 Ω DC input) DC to 100 MHz (1 MΩ DC input) 1.5 Hz to 100 MHz (1 MΩ AC input) | ||
Signal Risetime | 50 Ω input 1.7 ns; 20% to 80% 1 MΩ input 10 ns; 20% to 80% (from 50 Ω source) | ||
Timing and Control | |||
Gate width | >1 ns to 30 µs in 1-3-10 sequence switch selectable with a continuously variable ×1 to ×5 multiplier | ||
Sample Correlation | Less than 0.5% of the sample output due to trigger t remains at trigger t + 1 | ||
Delay | |||
Min Intrinsic Delay | 20 ns (ECL trigger input) 15 ns (ECL trigger input, delay board bypassed) | ||
Max Delay Range | 3 ns to 300 ns in 1-3-10 sequence plus user options, which give 10 µs (default), and 1 µs, 100 µs, 1 ms or 3 ms by capacitor change. | ||
Manual Adjustment | Screwdriver vernier control adjusts delay from 0.5 % to 100 % of range | ||
External Adjustment | 0 to 10 V DC varies delay by 0.5 % to 100 % of range | ||
Input | |||
Trigger | |||
Internal | 0.5 Hz to 40 kHz selectable with range switches 0.5, 5, 50, 500, 5000, off. Vernier is 10× range. | ||
External ECL | Positive edge, 5 ns min pulse width with termination of 50 W to -2 V; -5 V to +10 V pk-pk safe input | ||
External TTL | Negative edge, 20 ns min pulse width ; -5 V to +10 V pk-pk safe input | ||
Max. Trigger Rate | Max 80 kHz | ||
Trigger Indicator | LED lights when unit is triggered | ||
Trigger Generator | |||
Output | BNC TTL out on rear panel active in all trigger modes. Polarity set by jumper. | ||
Frequency ranges | 0.5, 5, 50, 500 Hz, 5 kHz and off with vernier to overlap ranges. | ||
Baseline Input | TTL line to indicate whether sample is signal or baseline value | ||
Analog Output Averager | |||
Modes | Linear or Exponential | ||
Samples Averaged | 1, 3, 10, 30, 100, 300, 1k, 10k | ||
LSO Droop Rate | < 0.2% FS/s | ||
Averager Droop Rate | When there are no triggers the droop rate is < 0.001% per minute for 10k samples | ||
Outputs | |||
Average out | ±10 V FS with 50 Ω output impedance and capable of driving a 2 kΩ load | ||
Last Sample out | ±10 V FS | ||
Gate Monitor | 0.3 V into 50 Ω to ground. Marker pulse-width equals gate width. Position is within 5 ns from actual gate | ||
Internal Rate Generator | TTL | ||
Baseline Output | TTL output line that toggles with each trigger to indicate whether next sample will be treated as a signal or baseline value. | ||
Power | +24 V at 200 mA -24 V at 150 mA | ||
+12 V at 300 mA -12 V at 590 mA | |||
+6 V at 160 mA -6 V at 630 mA | |||
Dimensions | |||
Height | 8¾" (222 mm) | ||
Width | 2¾" (70 mm) | ||
Depth | 9¾" (248 mm) | ||
Weight | 3 lb (1.4 kg) |
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